Fabrication of barrier material devices



Nov. 30, 1965 A. J. CAGGIANO 2 FABRICATION OF BARRIER MATERIAL DEVICESFiled Aug. 25, 1961 3 Sheets-Sheet 1 F/G 1b /0 ANTHONY J. CAG'G/A/VOATTORNEY Nov. 30, 1965 A. J. CAGGIANO FABRICATION OF BARRIER MATERIALDEVICES 3 Sheets-Sheet 5 Filed Aug. 25, 1961 lNVE/VTOR V w M m R wflwm m.A K 0 m M6 w United States Patent 3,220,895 FABRICATIGN 0F BARRIERMATERIAL DEVICES Anthony J. Caggiano, Newtonville, Mass., assignor toRaytheon Company, Lexington, Mass, a corporation of Delaware Filed Aug.25, 1961, Ser. No. 133,906 7 Claims. (Cl. 148-333) This inventionrelates generally to electrical translating devices and to methods oftheir manufacture and, more particularly, to barrier or semiconductivedevices in which junctions are formed in the body of the barrier orsemiconductive material.

A number of problems inherently reside in the fabrication ofsemiconductive devices, such as transistors, by the gaseous diffusionprocess. For example, in the prior art gaseous diffusion process, thesemiconductive slice is impregnated with the gaseous impurity on bothsurfaces resulting in the formation of two P-N junctions or transitionlayers, one on each side, and during the fabrication of a transistorfrom such a diffused slice one of these P-N junctions must be removed bygrinding or lapping resulting in the loss of material approximating onehalf of the original slice. Further, if the diffused junction is foundto be faulty the semiconductive slice cannot be reprocessed. Stillfurther, the diffusion process requires bulky, expensive equipment and aprocess time ranging from two to four hours. In addition, a problemexists in properly attaching and positioning the extrinsic baseresistance of the device to as low a value as possible consistent withother device parameters without causing shorting between the emitter andbase regions. Such diffusion techniques also require reliance uponvariable factors such as diffusion depth penetration, emitter depthpenetration and penetration of the base contact into the body of thesemiconductive material. All these factors require control and militateagainst the reproducibility of a given device structure.

Accordingly, the present invention is directed toward the realization ofa semiconductive device structure, which from its normal constructionmethod, minimizes or completely eliminates the effect of the variableemitter and base depth penetrations and achieves more closely controlledelectrical parameters. Other benefits over those of the diffusionprocess also occur; for example, since only one surface is processed nomaterial is lost through grinding or lapping and if improperly processedthe semiconductive slice can be quickly and easily salvaged. Also lessexpensive equipment is used and the time required for processing isreduced to approximately twenty minutes. Further, the beneficial resultsachieved by epitaxial growth can be realized without the necessity offollowing the epitaxial growth process. Still further, in devices of thepresent invention the semiconductive body is provided with alow-resistance metallic surface layer resulting in a low resistance pathwhich extends in close proximity to the emitter junction or transitionlayer and does not require accurate positioning of a base connection tothe layer. Preferably, these and other benefits are accomplished byfabricating the device from a body of semiconductive material which isprovided with a relatively thin surface layer of high conductivitymaterial. An emitter element containing an impurity material of oppositecon- 'ice ductivity type from that of the surface layer is positioned onthe surface layer. The assembly is then heated to a temperaturesufficient to melt both the surface layer and the emitter element (butnot to melt the semiconductive body) to cause them to penetrate or alloyinto the chip to produce the desired emitter and collector junctions ortransition layers having a base region between them which remains inelectrical contact with a highly conductive surface layer. It isbelieved that during alloying and regrowth process the metallicmaterials comprising the base region and the emitter region tend toremain substantially segregated from each other such that little or noclean-up by chemical or electrolytic etching between these two regionsare necessary to provide proper operation.

The invention will be better understood as the following descriptionproceeds taken in conjunction with the ac companying drawings wherein:

FIGS. 1a through 1h show a semiconductive device in various stages offabrication in accordance with the present invention;

FIGS. 2a through 2d show an alternative embodiment of a devicefabricated in accordance with the present invention;

FIGS. 3a through 30 show still another alternative embodiment of asemiconductive device in accordance with the present invention; and

FIG. 4 shows a pictorial view of a completed transistor after completionof the device has been effected by encapsulation of the device in asuitable housing.

Referring now to FIGS. 1a through 111, the process of fabrication of asemiconductive device will be describe in detail.

Although the particular example to be described has been found mostbeneficial when the semiconductive body comprises a silicon chip orwafer, it should be thoroughly understood that the invention can also beapplied to any other kind of semiconductive or barrier material as, forexample, germanium, germanium-silicon compounds, and other compoundsknown as inter-metallic compounds which are formed from element ofGroups III and V of the Periodic Table as, for example, galliumarsenide, indium antimonide, indium arsenide and the like, which haveresistivity ranges from 10- ohm-cm. to 10 ohm-cm. The term barriermaterial as used throughout the specification and claims is intended toinclude those materials having a forbidden energy band. In FIG. 1a thereis shown a body of silicon 10 which has been doped with an appropriateN-type (Group V) impurity such as phosphorous, or antimony. In theexample shown, the body 10 has a resistivity of approximately 2ohm-centimeters. The chip is next coated with a thin layer or element ofa P-type impurity material (Group III element), in this case, aluminum,to provide the layer 12 of highly conductive material on the surface ofthe chip 10. The aluminum layer may have a thickness ranging from about500 A. to about 3000 A., but for the present embodiment, the thicknessof the aluminum layer 12 (FIG. lb) is approximately 1000 A. It should benoted that the thickness of the aluminum layer is critical within limitssince a layer which is too thick will smear with the emitter elementduring the subsequent heating process and will also act to lower theforward current gain d of the finished unit. On the other hand, if thealuminum layer 12 is too thin, the extrinsic base resistance and otherparameters of the device will be deleteriously affected. The layer 12may be applied to the body 10 by a vapor evaporation and depositionprocess in accordance with techniques well known in the art, or by anyother suitable technique providing similar end results. For example,this may be accomplished by placing the body 14) into an evacuatedchamber having a 1O mm. vacuum and vaporizing aluminum from a hot Wirein the evacuated space such that the vaporized aluminum deposits on thebody 10. The thickness of the layer 12 being accurately controlled bycontrolling the deposition time and distance, or volume of the aluminumsource.

After deposition of the aluminum layer 12, the semiconductive body isremoved from the evacuated chamber and appears as shown in FIG. 1b inwhich the aluminum metal layer 12 is positioned on the upper surface ofthe body 10. If upon visual inspection this aluminum layer is found tobe faulty, then the layer may be easily stripped from the slice and theslice recoated. The next step, as shown in FIG. 10, in the processconsists in providing the body with an appropriate emitter element 13.To this end a pellet or dot 13 of an N-type impurity material (Group Velement) is placed on the aluminum layer 12. In the process beingdescribed, the dot or pellet 13 comprises a small cylinder approximately.005 inch to .010 inch in diameter and .0025 inch thick of an alloyconsisting of 99% silver and 1% arsenic. It should be thoroughlyunderstood that the use of a pellet or dot in such a case is onlydescriptive of the particular embodiment and that the same results canbe accomplished by vapor evaporation and deportion process or by othersuitable techniques in which appropriately doped materials are placedupon the surface of the layer 12 in the same manner as if a doped pelletwere placed thereon. With the pellet 13 positioned in place, theassembly is inserted into a conventional firing furnace and heated to atemperature of about 1150 C. for approximately five minutes at whichtime both the pellet 13 and the aluminum layer 12 are changed into amolten state. This temperature is above the eutectic point of the layer12 and the body 10. This phase of the process may be described asessentially an alloying phase. The temperature in the furnace is thenreduced to approximately 1100 C., which is below the eutectictemperature of the layer 12 and the body 10 but over the melting pointof the layer 12 and the pellet 13, and held at this temperature for atime period of approximately twenty minutes. After the above-describedheating cycle the assembly appears as 'shown in FIG. 1d in which thealuminum layer 12 has penetrated into the body 10' not only at thesurface region but also under the emitter pellet 13. The portion 14(FIG. 1e) under the pellet 13 comprises the active base region of thedevice and merges continuously into the surface layer portions therebyproviding a highly conductive appropriately doped metallic layer 12a atthe surface of the body 10 to which a subsequent base connection may beeasily made. It has been found that the width of the base region 12a issubstantially the same at the surface of the device and in the portion14 under the pellet 13. In the particular example in which the layer 12was approximately 1000 A. thick, the thickness of the resulting baseregion 14 is approximately 20,000 A. thick.

Although the action which takes place during the alloying phase of theheating process to form the emitter and base regions is not completelyunderstood, it is known that the greater portion of the base region isformed by a process of diffusion with the result that the base region isprovided with an impurity gradient across its width which enhances thehigh frequency response of the device due to the built-in electric fieldresulting from the distribution of the impurities. However, as to thealloying phase, it is believed that the layer of aluminum metal beneaththe emitter 13 appears to stay substantially segregated from thematerial composing the dot 13 and hence mony, tantalum or bismuth.

moves into the semiconductive body ahead of the emitter material.

While the mechanism by which this is accomplished is not completelyunderstood, it is believed that the following process occurs.

As the structure depicted by FIG. 1c is heated, the molten aluminumlayer 12 commences to dissolve the silicon immediately below it. Thisprocess continues throughout this aluminum layer 12 until this layer 12becomes saturated with silicon. At this point, no further penetration ofthe aluminum into the silicon 10 occurs, due to alloying. However, thealuminum layer 14 immediately under the emitter 13 is also undergoing asimilar process of dissolving silicon but does not become saturated withsilicon as rapidly as the surrounding layer. This is because of theeffect of the molten emitter 13 which becomes a sink for the dissolvedsilicon in the aluminum layer 12 below it and therefore, by diffusion,enables silicon to flow through this base layer 14 into the-emitter. Asthe emitter alloy becomes saturated with silicon, no further flowing ofsilicon through the base region 14 occurs, thus permitting the baseregion 14 to become saturated with silicon. At this point, noappreciable penetration by the aluminum base region 14 and the emitter13 occurs by the alloying process. The temperature is next reduced (a)to stop additional penetration and possible mixing of these metals, and(b) to provide a suitable junction or transition layer through regrowthand diffusion. It is during this latter step that considerable parameterimprovement occurs, thus providing addition- 211 control over thesubsequent characteristics of these devices. Experience with thisprocess indicates little or no absorption by the emitter 13 of thealuminum base layer 14 immediately below the emitter 1 3. This isevidenced by a relatively constant thickness of the base 14 and surface12 aluminum regions. This latter condition is also extremely importantin the control of base width, and hence transistor performance byinitial control of the aluminum evaporated thickness.

At this point in the process, a layer of material 15, impervious toetching, is applied to the emitter 13 and for a distance ofapproximately .005 inch to .010 inch beyond the emitter edge (FIGS. 1eand 1 The purpose of this coating is to permit the removal of excesssurface (FIG. lg) and the clean up of the collector to base diode.Essentially, this etching operation forms a pedestal 0r mesa of a heightslightly greater than the maximum penetration of the aluminum doped baselayer. The layer 15 (FIG. 1e) may be any suitable masking material, as,for example, a lacquer or wax. With the layer 15 in position, the chip10 may be immersed in an etching solution in order to remove thematerial outside the masked area and form the pedestal region 16 shownin FIG. 1g. The etching solution may comprise one part hydrofluoricacid, one part nitric acid solution and the chip may be immersed for atime period on the order of three seconds. After removal from theetching solution, the assembly is cleaned preferably in a four stepprocess which comprises dipping the chip successively into a solution ofpermachlor, then into an ethyl acetate solution, then into thepermachlor solution and finally into an alcohol rinse. After theclean-up procedure, appropriate leads (17, 18 and 11), as shown in FIG.1h, may be attached to the chip in order to form the external conductingleads of the device. The leads may comprise, for example, .005 inchdiameter gold wires which are bonded to the emitter, base and collectorregions.

Although there has been described herein a specific embodiment of an NPNtransistor, it should be thoroughly understood that PNP devices may alsobe made in the same manner using a slice of semiconductive materialwhich is properly doped and evaporating thereon a layer of suitableN-type doping material such as anti- It should also be understood thatsimilar devices may be made by using any barrier material.

Instead of separately forming the emitter base and collector electrodesof a device in accordance with FIGS. la through Ie, the process depictedin FIGS. 2a through 2d may be utilized. In this process, asemiconductive chip 20 is provided with a deposited layer of aluminum 21in a manner similar to that described with respect to FIGS. 11: through1g. An appropriate emitter pellet 22 as described above, is then placedon top of the layer 21 and a base pellet 23 of a suitable P-typematerial, for example of substantially pure aluminum is placed on top oflayer 21 at a point adjacent to the pellet 22. The aluminum pellet 23can be the form of a small cylinder approximately .005 inch in diameterand .001 inch thick. The chip 20 is placed upon a suitable conductingelement 24 which will form the collector connection of the finisheddevice. The element 24 may be a molybdenum tab. Between the tab 24 andthe body 20 a suitable impurity-doped preform may be placed comprising,for example, an element 25 comprised of tin and arsenic in order toprovide a substantially ohmic connection to the body 20. With theassembly arraged as shown in FIG. 2a it is then placed into a suitablefurnace and sent through the alloying and diffusion heating cyclesdescribed above with respect to FIG. 1 in order to cause the layer 21and pellets 22 and 23 to become molten and alloy with the body 20.

After the heating cycles are completed and the unit has cooled, itappears as shown in FIG. 2b in which the emitter pellet 22 and the basepellet 23 have alloyed into the body 20. The region 26 below the emitterpellet 22 comprises a diffused base region merging into the surfacelayer 21a similar to the region 14 (FIG. 1) which merges into thesurface layer 12a. As with the embodiment shown in FIGS. 1a through 1g,the emitter pellet 22 and the base pellet 23 is next masked with a layerof wax 27, and then subjected to the previously described etching step.After the etching step is completed, the wax layer is removed and theunit appears as shown in FIG. 2d in which the emitter and base pelletsrest on the pedestal 28 formed on the top surface of the chip 20. Leads29 and 30 may then be attached to the pellets in order to provideexternal connections.

As an alternate embodiment of the present invention a device may beprovided in which the area of the evaporated surface layer and the areaof the emitter layer is restricted prior to the heating cycle and onwhich an oxide layer is produced to protect the collector base junctionand the emitter base junction and to provide a lower C To this end asemiconductive ohip 40, as shown in FIG. 3a, is provided with a layer ofaluminum 41 which extends only over a limited surface area of the base40. This may be accomplished in one approach by vapor plating the layer41 onto the surface of the base 40 through a mask 42 which has anopening 43 through which the vaporized aluminum is directed. In thismanner only the portion of the chip 40 immediately below the opening 43becomes plated. After this plating is completed, the mask 42 is removedand a second mask 45, as shown in FIG. 3b, with an opening 46 is placedthereon. An emitter element 44 is then deposited on the layer 41 in thesame manner in which the layer 41 was deposited on the body 40. Theentire assembly is then placed in a furnace and put through the alloyingand diffusion heating cycle previously described in conjunction withFIG. 1. After the heating cycle is completed the unit appears as shownin FIG. 3!: in which the emitter 44 and the base 41 have alloyed intothe chip 40 and produced the diffused base region 51 below the emitter44. As can be seen, the surface or base layer 41 now extends only alimited distance across the top surface of the base 40 thereby reducingthe total area of the collector base junction 52 which produces the sameeffect as the pedestal etching step described with respect to theprevious embodiments. Following this heating cycle, a heavy oxide layer47, as shown in FIG. 3d, is placed over the entire surface of thedevice. This may be accomplished in any convenient manner such asfeeding into the furnace an atmosphere of wet hydrogen. The device isthen treated so as to reduce its temperature after which it is removedfrom the furnace. Thus, the method of FIGS. 3a through 30 eliminates theetching step which is necessary to form the pedestal on the top surfaceof the chip 40 and the oxide layer prevents any surface inversion layersor other contaminants from adhering to the surface and destroying theP-N junctions formed in the device. The oxide layer 47 is then brokenaway at selected portions over the emitter area 44 and the base area 41so that appropriate conducting leads 48, 49 and 50 may be attached tothe various regions to provide the connections to the externalconducting leads. In such an event the oxide layer 47 must be carefullycut away so that the collector to base junction 52 and the emitter tobase junction 53 is not exposed to the ambient.

Referring now to FIG. 4, there is shown a pictorial view of a transistorafter completion of the device has been effected by encapsulating thedevice within a suitable housing. The device could be any of those shownin the previous embodiments, but for the purposes of this description aunit such as described in FIGS. 2a through 2b is shown. In this devicethe chip 20 attached to the molybdenum tab 24 is mounted on a pair ofsupporting posts and 61. One of these posts 60 extends through the stemportion 63 of the device. Conducting posts 64 and 65 also extend throughthe stem 63 and leads 29 and 30 are connected thereto in any suitablemanner as by soldering or welding. The housing 66 is attached to theflange 63a of the stem portion 63 at the bottom thereof in order tohermetically seal the device 20 within the outer housing. The externalleads 60, 64 and 65 are suitably insulated from the stem 63 by a glassmedium 31 around each lead.

This completes the description of the preferred embodiment of theinvention. However, many modifications of the invention will be apparentto persons skilled in the art. Accordingly, it is desired that thisinvention not be limited except as defined by the appended claims.

What is claimed is:

1. A transistor device comprising a body of semiconductor material ofone conductivity type comprising a collector region, said body having asurface, a base region of a different conductivity type positionedwithin said body, said base region and collector region forming ajunction at their point of intersection, said collector-tobase junctionhaving its terminus at said surface of said body, an alloyed emitterregion of the same conductivity type as said collector region positionedwithin said base region and said body, said emitter region forming aj-unction with said base region, said base-to-emitter junction havingits terminus at said surface of said body, said base region having apartially diffused portion underlying the emitter region and theremainder of said base region having an alloyed portion with a topexposed surface having the resistivity of a conductor which merges intosaid partially diffused portion, a contaminative protective coatingcovering said junction terminus, and contacts connected to said regions.

2. A device according to claim 1 wherein said base region comprises ametallic conducting material.

3. A device according to claim 1 wherein said surface is a planesurface.

4. A device according to claim 3 wherein said coating is an oxide layer.

5. A device according to claim 4 wherein said base and emitter contactspass through openings in said oxide layer to form base and emitterconnections with said base and emitter regions, respectively.

6. A device according to claim 5 wherein said base region underlyingsaid emitter region comprises a partially diffused and partially alloyedimpurity gradient structure.

7. A device according to claim 1 wherein said base region underlyingsaid emitter region comprises a .pa1'- tially diffused and partiallyalloyed impurity gradient portion.

References Cited by the Examiner UNITED STATES PATENTS 4/1956 Barnes14833 2,899,344 8/1959 Atalla 14'8-l-.5 2,970,896 2/1961 Cornelison1481.5

' 3,010,855 11/1961 'Barson 1481.5

, 3,029,170 4/1962 Lamming 1481.5 5 3,074,826 1/1963 Tum-mers 148-1.5

OTHER REFERENCES Jochems et al.: Construction and Electrical Propertiesof a Germanium Alloy-Diffused Transistor}? Proceedings 10 of the IRE,June 1958, pages 11611165.

DAVID L. RECK, Primary Examiner. -WINSTON A. DOUGLAS, Examiner.

1. A TRANSISTOR DEVICE COMPRISING A BODY OF SEMICONDUCTOR MATERIAL OFONE CONDUCTIVITY TYPE COMPRISING A COLLECTOR REGION, SAID BODY HAVING ASURFACE, A BASE REGION OF A DIFFERENT CONDUCTIVITY TYPE POSITIONEDWITHIN SAID BODY, SAID BASE REGION AND COLLECTOR REGION FORMING AJUNCTION AT THEIR POINT OF INTERSECTION, SAID COLLECTOR TOBASE JUNCTIONHAVING ITS TERMINUS AT SAID SURFACE OF SAID BODY, AN ALLOYED EMITTERREGION OF THE SAME CONDUCTIVITY TYPE AS SAID COLLECTOR REGION POSITIONEDWITHIN SAID BASE REGION AND SAID BODY, SAID EMITTER REGION FORMING AJUNCTION WITH SAID BASE REGION, SAID BASE-TO-EMITTER JUNCTION HAVING ITSTERMINUS AT SAID SURFACE OF SAID BODY, SAID BASE REGION HAVING APARTIALLY DIFFUSED PORTION UNDERLYING THE EMITTER REGION AND THEREMAINDER OF SAID BASE REGION HAVING AN ALLOYED PORTION WITH A TOPEXPOSED SURFACE HAVING THE RESISTIVITY OF A CONDUCTOR WHICH MERGES INTOSAID PARTIALLY DIFFUSED PORTION, A CONTAMINATIVE PROTECTIVE COATINGCOVERING SAID JUNCTION TERMINUS, AND CONTACTS CONNECTED TO SAID REGIONS.